1. Field of the Invention
The present invention relates to a data processing apparatus and method for fetching an instruction in to an instruction cache, and in particular to such a data processing apparatus and method that enables an instruction to be pre-fetched in to an instruction cache without that instruction being passed to a processor core within the data processing apparatus for execution.
2. Description of the Prior Art
Typically, a data processing apparatus, such as a microprocessor, is arranged to apply instructions received to data items read from memory, a processor core being provided within the microprocessor to process the instructions. In order to reduce the number of accesses required to memory in order to retrieve the instructions and the data, it is known to provide one or more caches which are accessible to the processor core. One approach is to provide a single cache for storing both instructions and data required by the processor core, such an arrangement being known as a Von Neumann architecture. However, alternatively, a separate instruction cache can be provided for storing instructions, and a separate data cache be provided for storing data values, such an arrangement being known as a Harvard architecture.
With the Von Neumann architecture, the processor core is able to execute certain instructions in order to pre-fetch either instructions or data values into the single cache prior to those instructions or data values being required by the processor core, such a process being known as a pre-fetch process. Similarly, with regard to the data cache in a Harvard architecture arrangement, the processor core again is able to execute certain "load" instructions in order to pre-fetch data values for storage in the data cache.
However, with regard to the instruction cache of a Harvard architecture arrangement, it is generally not possible to add an instruction to the instruction cache without that instruction being returned to the processor core, and added to the pipeline for subsequent processing by the processor core. This is because whenever the processor core outputs an instruction address on an instruction address bus to the instruction cache, it will also issue a predetermined control signal to the instruction cache to cause the instruction cache to perform an instruction fetch procedure, this ultimately resulting in the fetched instruction being output on an instruction data bus back to the processor core for subsequent execution by the processor core.
Hence, it is an object of the present invention to provide a data processing apparatus and method which enables instructions to be pre-fetched into an instruction cache without those instructions being returned to the processor core for subsequent processing by the processor core.